The present invention relates in general to semiconductor technology, and more particularly, to structures and methods for forming semiconductor devices in shielded and non-shielded gate trench field effect transistors (FETs) with minimum cell pitch.
To increase transistor packing density of trench FETs, it is desirable to minimize the trench width as well as the mesa width (i.e., the spacing between adjacent trenches). However, both of these dimensions are limited by constraints imposed by manufacturing equipment, structural requirements, alignment tolerances, and transistor operational requirements. For example, the minimum width of the mesa region between adjacent trenches is limited by the space required for forming source and heavy body regions. Alignment tolerances associated with forming the trenches and the source and heavy body regions further limit cell pitch reduction.
Many techniques for reducing the cell pitch of trench FETs have been proposed, but none have been able to achieve a substantial reduction in cell pitch without significantly complicating the manufacturing process or adversely impacting transistor performance.
Thus, there is a need for a technique whereby the cell pitch of trench FETs can be reduced while maintaining a simple manufacturing process and superior transistor performance.